As is known in the art, DACs are used widely in variety of applications to convert an N-bit digital word to a corresponding analog signal, typically a voltage signal. Currently, there are a number of DAC architectures based on different conversion techniques to convert the N-bit digital word to a corresponding voltage signal. Voltage-scaling DACs, current-scaling DACs, charge-scaling DACs, and a combination of voltage and current scaling DACs are just a few examples of current conversion techniques used in the DAC architectures.
The current-scaling DACs can be power hungry due to the requirement of an additional current-to-voltage conversion element Such current-scaling DACs are generally not suitable for applications requiring low power and small chip area The charge-scaling DACs generally have a leakage and hence can require a frequent charge refresh. Therefore, such charge-scaling DACs are generally not suitable for applications where there is no free running clock to refresh the charge. Moreover, a free running clock can introduce undesirable noise in the output.
Whereas, the voltage-scaling DACs have high accuracy, high speed, monotonocity, and low power requirement and therefore are generally widely used. A typical N-bit voltage scaling DAC comprises of a single resistor string of (2**N) resistors of value R and a switching network to couple the voltage at one of the resistors to an output to produce the converted voltage. While such DAC architecture is suitable for applications where N is relatively small, when N is large, the number of resistors and switches required increases exponentially and hence can significantly increase the required chip area, thus making it not suitable for applications requiring small chip area.
One technique suggested to reduce the number of elements in a single resistor string converter is to use a segmented dual string converter. In the segmented dual string, a first stage uses a resistor string for converting a group of higher order bits in the N-bit digital word and a second stage decodes the remaining lower order bits. A non-linear converter of this type is shown in an article by Gryzbowski et al., entitled “Non-linear Functions from D/A converters”, Electronic Engineering 1971, pgs. 48-51. The converter presented in this article is designed for operation with relay switching and is not readily adaptable to modem semiconductor technology.
While the current segmented dual string techniques are useful in many applications. They still require relatively higher number of resistors and switches in the first and second stages thereby requiring a relatively large chip surface area during fabrication. In addition, the capacitance also increases due to the higher number of switches. Increased capacitance can result in lower speed and performance. For example, a 16-bit resolution DAC having 8 bits in the primary string and 8 bits in the secondary string requires 513 switches and 511 resistors (i.e., (29+1) resistors and (29−1) switches). Further, to go to a higher resolution, for example, going from a 16-bit resolution to a 20 bit resolution, the number of switches required for every bit increases by a factor of 21/2. Therefore, going from the 16-bit resolution to the 20-bit resolution increases the number of required switches by a factor of 4, i.e., the number of required switches increases from 513 switches to 2049 switches. This can result in an extendibility problem. In addition, in all types of segmented resistor string DACs, the on-resistance of the switches used in the switching network plays an important role in determining the differential non linearity (DNL) of the segmented resistor string DACs. In general, the higher the on-resistance, the higher will be the DNL of the segmented resistor string DACs. Therefore, increasing the resolution can not only increase required chip area but can also increase time constant, i.e., resistance and capacitance in a signal path, which in-turn can result in lower speed and performance.